The need for a fast-acting circuit for reading data from and writing data into the memory cells, in particular, those that buffer packet data is described briefly in U.S. Pat. No. 5,309,395 issued May 3, 1994 entitled "Synchronous Static Random Access Memory". The '395 patent solved the speed problem by providing circuitry for reading lo from and writing into a memory unit in a single memory cycle. The circuitry included a precharge circuit, a pair of cross-coupled sense amplifiers, a latch generator, a read latch and a write circuit. As shown in FIG. 5 of the '395 patent, during a first half-cycle, (t.sub.0 -t.sub.1), of a clock defining the memory cycle, a precharge circuit charged a pair of 0-bit and 1-bit lines threading through the memory array at the same time the sense amplifiers were clamped to produce a balanced output. At the end of the first half-cycle the precharging of the bit lines terminated. During the second half-cycle of the clock, a word was selected in the memory and a path was completed to allow the sense amplifiers to draw current from the bit lines. After a self-timed delay, (t.sub.1 -t.sub.2) provided by analog circuit elements, the clamping of the sense amplifiers was removed allowing the amplifiers to follow the voltage changes on the bit lines as determined by the stored binary information state of the selected word. During this interval, cross-coupling between the amplifiers provides positive feedback which rapidly amplifies the small voltage difference on the bit lines into complimentary logic states on the outputs of the sense amplifiers. During the final interval, (t.sub.3 -t.sub.4), the sense amplifiers generate a signal to latch the data read out and to allow new data to be written into the memory cells. It was the provision of a common latch signal to the read latch circuit and to the write circuit that enabled the circuit of the '395 patent to perform both a read and a write operation on a memory cell within a single half-cycle of the memory clock. A stated advantage of the '395 patent circuitry was that its regeneratively cross-coupled amplifiers only slightly discharged the bit lines during a read operation and thereafter drew only negligible current from the bit lines once the contents of the memory cells had been read. Leaving the bit lines close to the supply potential facilitated the rapid precharging of the bit lines after the sensing operation was completed.
While the circuitry of the '395 patent functioned satisfactorily in many applications, and had low power drain once the memory cell contents was read, its cross-coupled amplifiers did draw a significant amount of current from the bit lines during the precharging and sensing portions of the memory cycle in order to attain fast operation. It would be advantageous to have a sense amplifier that drew less current from the bit lines and which, accordingly, would offer lower power consumption than that of the '395 patent. It would also be advantageous to reduce the complexity of the overall circuitry by eliminating the need for a separate latch circuit.